We post major updates and a periodic summary to the mailing list.
While it is possible to regenerate the schematics from the CAD files, we want to allow users to easily access the detailed schematics of the entire Enzian system. The complete board schematics for Enzian revision 1.5c have now been released.
As part of the ASPLOS Paper, we submitted two artifacts to demonstrate the work. The first was the entire collection of CAD files necessary for remanufacturing (or improving!) the Enzian board. The second artifact was used by the AEC reviewers to confirm that the results we presented in the paper were reproducable. As mentioned previously, we are very happy that we received all three badges, including the coveted “Results Reproduced”.
We’re happy to announce that we’ve made the original design sources for Enzian available for free download from Zenodo.
We’ve managed to post 3 new “technical nuggets” to the web site - little snippets of technical information about and around Enzian, which are quicker to write and post than full documentation, but will hopefully find themselves into the user manuals in due course:
We’re delighted to announce that our paper on the design of Enzian has been accepted (subject to final shepherding) to the 27th ACM Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), to be held (hopefully) in Lausanne next month!
We’ve finally made an update to the Enzian web site - the first of many this year, we hope!
A couple of weeks ago, we presented Enzian at the Industry-Academia Partnership (IAP) University of Washington University/UC Berkeley/NYU Workshop on the Future of Cloud Computing Applications and Infrastructure.
Coyote, our first candidate for an operating system for FPGAs, was presented by Dario Korolija last week at OSDI 2020. You can read the paper, look at the slides, and watch Dario’s presentation online here.
We are delighted to announce that the first single-board Enzian machine is working! Here is a picture of the first working board:
Today had a few white-knuckle moments with power sequencing, but in the end this has been a really great day!
A somewhat nerve-wracking time in the Enzian team as the Swiss lockdown is relaxed:
When we got the first boards back late last year, they were not functional - in particular, an error in the design made it impossible to power up the FPGA or CPU. This was caught by the company doing the assembly, so we didn’t have the two big chips soldered on.
We’ve been pretty quiet about Enzian over the last few months, but plenty has been happening behind the scenes despite the difficult times we’re going through. Best wishes for good health to everyone reading this.
In October we had a paper on Enzian accepted to CIDR 2020 - the Conference on Innovative Data Systems Research, held in Amsterdam this January!
It’s been a long time since we posted an update to the Enzian site, for which we apologize! It’s not that little has been happening - quite the opposite!
We have a first run of fabricated test boards for Enzian. Here’s what they look like (with pen for scale):
Here’s a 3D render of the eATX-format Enzian board.
We’ve now got a power distribution board back from manufacture. David designed this to help us build a mock-up Enzian power and clock distribution network so Adam can write and test the Board Management Controller software.
We’ve finalized the schematic for the first revision of the Enzian single board, and Dream Chip have now started PCB layout. Many thanks to everyone at ETH, Cavium, and Xilinx who helped review the draft schematics and spot issues!
Prof. Mothy Roscoe gave a talk at the Dagstuhl seminar on “Convergence in Networked Systems”.
Thanks to Zeke, we now have a working DDR4 controller for the FPGA-side of Enzian integrated with the (prototype) donut/shell.
Thanks to some great TianoCore hacking from Adam, we now have Linux (and Barrelfish…) reliably booting on the ThunderX side of the Enzian prototype machines! This also gives us a solid software base for booting the final production board when it arrives.
We’ve successfully applied to the IEEE for an Organizationally Unique
Identifier (OUI), since we’re going to need at least 7 MAC addresses
per Enzian system (1 for the BMC, 2 for the ThunderX, and at least 4
for the FPGA 100Gb/s interfaces). Enzian how has a Large MAC address
Prof. Mothy Roscoe gave the “Red Hat Collaboratory at Boston University Colloquium” on April 19th and presented the following day at the IAP workshop at MIT.