We’ve been pretty quiet about Enzian over the last few months, but plenty has been happening behind the scenes despite the difficult times we’re going through. Best wishes for good health to everyone reading this.
On the hardware design side, Dream Chip got the second spin of the boards back manufacturing a few weeks ago, and while they found some minor bugs they could all be fixed by patching, and so we’re expecting them back from assembly in the next week or so. Fingers crossed.
Despite the lockdown in Switzerland, there’s been a ton of work at ETH on programming the FPGA, and on the Enzian Coherence Interface (ECI) as we call our implementation of the inter-socket cache protocol. We’ve fixed an annoying bug that was causing periodic machine checks, and there’s now a lot of momentum behind building higher-level functions over the basic protocol.
We’ve also been working on various parts of the software and development environment for Enzian, including simulators both for the CPU and FPGA sides.
We’ll post more detailed stories, in no particular order, over the next few days.
In the meantime, here’s a picture of what things looked like before ETH Zurich closed its doors and went completely online due to Coronavirus: Michael Giardino building part of the our rig for signal integrity testing. Our field is Systems Software - we didn’t expect our offices to look like this when we started: