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Declarative Power Sequencing using a CPLD
- Manuel Hässig
Bachelor's Thesis, ETH Zürich,
February 2022
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Generating Power Management Code from Declarative Descriptions
- Linus Vogel
Bachelor's Thesis, ETH Zürich,
October 2021
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Optimizing Declarative Power Sequencing
- Moritz Knüsel
Master's Thesis, ETH Zürich,
September 2021
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Towards Trustworthy BMC Software on Modern Hardware
- Ben Fiedler
Master's Thesis, ETH Zürich,
August 2021
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High-speed Tracing of Coherence Traffic using FPGAs
- Manuel Bröchin
Master's Thesis, ETH Zürich,
August 2021
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Real-time Board Management using an FPGA
- Sarah Tröndle
Bachelor's Thesis, ETH Zürich,
April 2021
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Towards high-assurance Board Management Controller software
- Cedric Heimhofer
Master's Thesis, ETH Zürich,
March 2021
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Computer platform visualization for Enzian
- Patrick Wicki
Bachelor's Thesis, ETH Zürich,
March 2021
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A model-based approach to platform-level power and clock management
- Jasmin Schult
Bachelor's Thesis, ETH Zürich,
August 2020