Who are we?

Current group members:

David Cock

Team lead, board design coordination, early board design, low-level ECI implementation, debug and trace infrastructure, lots of soldering.

Adam Turowski

Barrelfish, Linux, and FreeBSD OS bringup, BMC software lead

Ben Fiedler

Formal verification of BMC software

Michael Giardino

Circuit testing, fabrication, power management, benchmarking

Zhenhao He

RDMA and TCP stacks

Dario Korolija

FPGA Shell design and implementation

Tom Kuchler

Hardware protocol analysis and filtering for ECI

Abishek Ramdas

Cache coherence implementation

Anastasiia Ruzhanskaia

Dataflow acceleration usecases

Daniel Schwyn

BMC and power management software


Reto Achermann

Trace processing, software emulation, Barrelfish bringup

Joel Busch

Detailed ECI cache simulation in ARM FAST models

Alain Denzler

Memory controller feasibility study

Tobias Grosser

Application use cases

Alexander Hedges

Simulation environment

Cedric Heimhofer

SEL4 on the BMC

Zsolt István

FPGA network stack and doughnut prototyping

Amit Kulkarni

Infrastructure and Verilog hacking

Nikita Lazarev

Interconnect protocol specification and modelling

Jialin Li

ARM FAST models ECI cache simulator

Kristina Martšenko

System power and performance modeling, benchmarking

Jakob Meier

Automated ECI trace analysis

Muhsen Owaida

ECI link bringup

Pirmin Schmid

Runtime verification on FPGAs

Jasmin Schult

Formal BMC firmware specification and synthesis of power sequencing

David Sidler

FPGA network implementation

Zeke Wang

DDR4 controllers and doughnut prototyping

Patrick Wicki

Platform visualization and monitoring

Patrick Ziegler

Hardware simulator integration

Industry partners




Other sponsors

HP Enterprise