Enzian is a research computer built by the Systems Group at ETH Zurich.
As a research computer, Enzian is designed for computer systems software research and deliberately over-engineered. Enzian has a big server-class CPU closely coupled to a large FPGA, with ample main memory and network bandwidth on both sides.
Thanks to the hard work of a bachelor’s student, Diego de los Santos, we have brought up the Rocket RISC-V core on the Enzian’s FPGA. We are able to load an image from the CPU side, across ECI, directly into the FPGA’s DRAM. We can then boot into Linux on the RISC-V core. While clock speed is obviously limited in the FPGA implementation (currently 100MHz) this is still many orders of magnitude faster than RTL simulation. This allows us to run more realistic, larger memory benchmarks on RISC-V. We can then examine power and performance implications of various microarchitectural changes.
As we explained in our post about the Enzian rear panel there are two client USB ports on Enzian: one for the JTAG scain chain and one for the system UARTs. The JTAG chip on the Enzian main board has a pre-configured JTAG cable ID that is unique. The serial-to-USB converter by default does not have a unique ID though. If you just plug one Enzian into your machine that does not matter, however we have 9 of these machines all plugged into our gateway server.
We built Enzian to have a platform for our research into operating systems, databases, hardware acceleration, machine learning, networking, and high-performance computing, and because there was nothing comparable out there that we could get hold of otherwise.
Now that it works, we’d like to make Enzian systems available to the rest of the research community. If you want to work with Enzian, or if you might be able to help us make it more widely available, please contact us!