Enzian tech nuggets

Interesting technical details about Enzian.

An overview of the BMC

In this post, we take a deeper dive into the BMC hardware and how it is connected to the Enzian’s mainboard.

The Enzian 3 v1.5 rear panel

In this post, we’ll take a look at the back of an Enzian system.

So, how fast is ECI really?

ECI is the Enzian Coherent Interconnect, our implementation of the cache coherence protocol that connects the XCVU9P FPGA on an Enzian board to the Marvell Cavium ThunderX-1 CPU.

Booting Enzian pt. 1: The BMC

This is the first post in a series where we look at how Enzian boots. In future posts we will look at the many stages the CPU and FPGA go through before we end up with a fully operational Enzian with the ECI coherency links up.

Adventures in Cache Coherence Interoperability

As we’ve said many times, a key feature of Enzian as a research computer is the low-level access to the cache coherency protocol, which in our case is the native inter-socket protocol implemented by the ThunderX-1 CPU.

Enzian and cache coherency

The role of cache coherency in Enzian is interesting to think about. Consider a typical two-socket NUMA machine (such as the kind of system that the ThunderX-1 processor was designed for):

Signal integrity testing

Testing the assembled, non-functional Enzian board for signal integrity turned out to be rather more work than we expected, much of it involving machining bits of metal – real hardware.

Results from the first test boards

We posted pictures of the first test PCBs back in August. Dream Chip sent two of these for assembly to see if they worked - a couple of issues had already been identified but they weren’t necessarily critical.