The CPU is up!

Today had a few white-knuckle moments with power sequencing, but in the end this has been a really great day!

  Cavium SOC
  Locking L2 cache
  PASS: CRC32 verification
  Transferring to thread scheduler
  ERROR: Invalid FDT header read from /boot
  WARNING: ****
  WARNING: * Board manufacturing information not found.  Program
  WARNING: * the board manufacturing information in the Setup menu.
  WARNING: ****
  Cavium Boot Stub
  Firmware Version: 2020-04-02 23:59:21
  BDK Version: a47ea60-dirty, Branch: heads/master, Built: Thu Apr 2 23:59:18
  TC 2020
  Board Model:    unknown
  Board Revision: unknown
  Board Serial:   unknown
  Node:  0
  SKU:   CN8890-2000BG2601-NT-Y-G
  L2:    16384 KB
  RCLK:  300 Mhz
  SCLK:  300 Mhz
  Boot:  SPI24(5)
  VRM:   Disabled
  Trust: Disabled, Non-secure Boot
  CCPI:  Disabled
  Boot Options
  S) Enter Setup
  E) Enter Diagnostics, skipping Setup
  F) Select Image from Flash
  X) Upload File to FatFS using Xmodem
  W) Burn boot flash using Xmodem
  U) Change baud rate and flow control
  R) Reboot

FPGA also checks out. Still to test: DDR4 and the coherence links, but it looks like we might be getting there.

“…and there was much rejoicing.”