Enzian updates

We post major updates and a periodic summary to the mailing list.

Enzian at the seL4 Summit 2022

The seL4 Summit took place earlier this month in Munich, and the Enzian team was represented by Daniel Schwyn, giving a talk about Trustworthy BMCs (recording available here).

RISC-V on Enzian

Thanks to the hard work of a bachelor’s student, Diego de los Santos, we have brought up the Rocket RISC-V core on the Enzian’s FPGA. We are able to load an image from the CPU side, across ECI, directly into the FPGA’s DRAM. We can then boot into Linux on the RISC-V core. While clock speed is obviously limited in the FPGA implementation (currently 100MHz) this is still many orders of magnitude faster than RTL simulation. This allows us to run more realistic, larger memory benchmarks on RISC-V. We can then examine power and performance implications of various microarchitectural changes.

Enzian Poster Accepted at OSDI

Our poster on recent Enzian work has been accepted at OSDI 2022! The OSDI 2022 poster session is from 18:30-20:00 on Monday 11 July, 2022. If you’re going to be at OSDI/ATC, please stop by and we can talk about new and exciting developments in person! We’ll update this post with a final version of the poster when it is available.

Enzian Schematics Released

While it is possible to regenerate the schematics from the CAD files, we want to allow users to easily access the detailed schematics of the entire Enzian system. The complete board schematics for Enzian revision 1.5c have now been released.

Enzian ASPLOS Software Artifact Publicly Released

As part of the ASPLOS Paper, we submitted two artifacts to demonstrate the work. The first was the entire collection of CAD files necessary for remanufacturing (or improving!) the Enzian board. The second artifact was used by the AEC reviewers to confirm that the results we presented in the paper were reproducable. As mentioned previously, we are very happy that we received all three badges, including the coveted “Results Reproduced”.

Our ASPLOS presentation!

A couple of weeks back, we presented our paper Enzian: An Open, General, CPU/FPGA Platform for Systems Software Research at ASPLOS 2022. The paper is now available in the ACM Digital Library.

ASPLOS Artifact Evaluation badges

As far as we can tell, our forthcoming ASPLOS 2022 paper, Enzian: An Open, General, CPU/FPGA Platform for Systems Software Research, has been awarded all three available Artifact Evaluation badges:

Board sources released!

We’re happy to announce that we’ve made the original design sources for Enzian available for free download from Zenodo.

Three technical updates

We’ve managed to post 3 new “technical nuggets” to the web site - little snippets of technical information about and around Enzian, which are quicker to write and post than full documentation, but will hopefully find themselves into the user manuals in due course:

ASPLOS paper accepted!

We’re delighted to announce that our paper on the design of Enzian has been accepted (subject to final shepherding) to the 27th ACM Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), to be held (hopefully) in Lausanne next month!

Enzian web site finally updated

We’ve finally made an update to the Enzian web site - the first of many this year, we hope!

Enzian demo video from the IAP Cloud Workshop now online

A couple of weeks ago, we presented Enzian at the Industry-Academia Partnership (IAP) University of Washington University/UC Berkeley/NYU Workshop on the Future of Cloud Computing Applications and Infrastructure.

Coyote paper presented at OSDI 2020

Coyote, our first candidate for an operating system for FPGAs, was presented by Dario Korolija last week at OSDI 2020. You can read the paper, look at the slides, and watch Dario’s presentation online here.

The first Enzian single board is working!

We are delighted to announce that the first single-board Enzian machine is working! Here is a picture of the first working board:

The CPU is up!

Today had a few white-knuckle moments with power sequencing, but in the end this has been a really great day!

Enzian power on test teaser

A somewhat nerve-wracking time in the Enzian team as the Swiss lockdown is relaxed:

Assembled Enzian v.1.3 board

When we got the first boards back late last year, they were not functional - in particular, an error in the design made it impossible to power up the FPGA or CPU. This was caught by the company doing the assembly, so we didn’t have the two big chips soldered on.

Long-overdue updates

We’ve been pretty quiet about Enzian over the last few months, but plenty has been happening behind the scenes despite the difficult times we’re going through. Best wishes for good health to everyone reading this.

Paper on Enzian accepted to CIDR 2020

In October we had a paper on Enzian accepted to CIDR 2020 - the Conference on Innovative Data Systems Research, held in Amsterdam this January!

Updates, at last!

It’s been a long time since we posted an update to the Enzian site, for which we apologize! It’s not that little has been happening - quite the opposite!

We have a board, sort of...

We have a first run of fabricated test boards for Enzian. Here’s what they look like (with pen for scale):

Board render!

Here’s a 3D render of the eATX-format Enzian board.

Team update

It’s been a while since we updated list of team members for Enzian.

Enzian power distribution boards

We’ve now got a power distribution board back from manufacture. David designed this to help us build a mock-up Enzian power and clock distribution network so Adam can write and test the Board Management Controller software.

We've signed off on the schematic

We’ve finalized the schematic for the first revision of the Enzian single board, and Dream Chip have now started PCB layout. Many thanks to everyone at ETH, Cavium, and Xilinx who helped review the draft schematics and spot issues!

Mothy gave a talk at Dagstuhl

Prof. Mothy Roscoe gave a talk at the Dagstuhl seminar on “Convergence in Networked Systems”.

FPGA-side DDR4 controller

Thanks to Zeke, we now have a working DDR4 controller for the FPGA-side of Enzian integrated with the (prototype) donut/shell.

Linux is up!

Thanks to some great TianoCore hacking from Adam, we now have Linux (and Barrelfish…) reliably booting on the ThunderX side of the Enzian prototype machines! This also gives us a solid software base for booting the final production board when it arrives.

We have an OUI!

We’ve successfully applied to the IEEE for an Organizationally Unique Identifier (OUI), since we’re going to need at least 7 MAC addresses per Enzian system (1 for the BMC, 2 for the ThunderX, and at least 4 for the FPGA 100Gb/s interfaces). Enzian how has a Large MAC address block assigned: 0C:53:31.

Mothy gave talks at Boston University and MIT

Prof. Mothy Roscoe gave the “Red Hat Collaboratory at Boston University Colloquium” on April 19th and presented the following day at the IAP workshop at MIT.